I don’t think it’s that easy and simple. While this may apply to current asic designs (cheap designs) i doubt it would be the same with really good designs.
Just as a theory example as i’am indeed not an asic/fpga hardware expert:
- An Asic design is made with easy software update function.
- The Asic has free unused slots for memory upgrades.
- Memory upgrades are produced as plug&play.
- Eventually other critical components are upgradeable as well.
This would only rise a given cost factor, not? Which for companies with big pockets woulddn’t be a real problem. Instead of having a doorstop asic you invest another USD 200-500 for example to upgrade it and are in the race/game again?
As said, just a more or less logical thought of mine and i would like to hear a comment from someone that has good hardware knowledge to see if this would be possible at all.
Edit: What for example would happen if there was an easy way to make the Z9/Z9 mini upgradeable with 10x the memory it currently has? What would be the result? Would it be able with some software/firmware tweaks to mine on 144_5 or 192_7?
Maybe questions for @mistfpga