Little is publicly known about the nature of the ASICs in a Z9. I’m personally quite curious how it deals with the memory bottleneck. The intent of a memory hard PoW is that it would use more memory than can fit on a single chip, so that an ASIC would have to use off-chip memory and performance would be constrained by the bandwidth and power consumption of all those IO pins.
Perhaps we can analyze whether the given Z9 performance is consistent with such an approach. Let’s see how much data needs to be read and written in one second.
10k solutions corresponds to solving 10k/1.88 instances, each of which needs to read/write 145 MB for 9 rounds, so that’s roughly 7 TB (3.5 TB written and 3.5 TB read).
Can DDR4 or LPDDR4 DRAM do that while consuming under 300 Joules?
If not, then the Z9 would have to avoid off-chip communication.
So this question is important for determining whether a change in Equihash parameters, e.g. to (144,5) will reduce the efficiency of future ASIC miners.
Update: This article
suggests it’s possible with HBM memory. But it would require the ASIC to consume a small fraction of the power of the memory IO.
I also found this paper
which gives 70 J/TB for DDR3 and 40 J/TB for LPDDR2,
and only 3.7 J /TB for Micron HMC DRAM reads.