All of the recent discussions about the benefits and weaknesses of various mining hardware such as GPUs, FPGAs and ASICS gave me the idea of trying to develop my own low cost SoC FPGA for Equihash mining.
I’ve decide to use the Terasic DE10-nano development board which is a low cost FPGA designed for academia. It is based off of the Altera Cyclone V - 5CSEBA6U2317. I chose this board for it’s a lost cost and energy efficiency. ThE DE10-nano is a SoC FPGA with a dual core 800mhz ARM processor, 1GB of DDR3 and 110K logic elements for $130 USD.
A few modifications have to be done to the board which include a heat sink and fan as the ARM processor will get quite warm under load. At this point in the project I’m still assembling the device hardware, but I hope to get working on some actual HDL pretty soon.
That being said, I’m pretty new to HDL design and implementation, but I have over 12 years experience in software development. I expect my progress to be fairly slow as this will also be a learning opportunity for me. At worst, I think this project could serve as a proof of concept and provide an opportunity to develop an extremely efficient equihash HDL implementation that could then be translated to more powerful FPGA equipment.
My primary goals are:
To facilitate my own learning about SoC FPGA development
To create an Altera Cyclone V implementation of equihash.
If anyone is interested in helping or supporting this project please feel free to contact me, any help is much appreciated.
I’m currently using Quartus Prime 18.0 Lite Edition, which I believe is Verilog. As I mentioned in my first post, I’m new to FPGA so I still have quite a bit to learn. If you’d like to help out it’d be much appreciated. Do you already have an Altera Cyclone 5 board?
For those following the project, this past week I’ve been working to modify my DE10-nano FPGA so that it can better handle the demands of the equihash algorithm. Here are some before and after pictures of my DE10-nano.
If anyone out there is interested in creating this piece of hardware please let me know so I can direct you to the appropriate channel to order the necessary parts. Now that I’ve completed the hardware setup, I plan to continue my Verilog studies and begin reviewing the bitstream for a BTC miner that runs on an older DE0 board that’s quite similar to the Altera Cyclone V used in the DE10-nano.
Thanks to all of you out there who have reached out and offered to give me a hand or participate in the project in some capacity, I greatly appreciate the support and help!
Board looks great man, I downloaded the Quartus ide to mess around a bit. Definity send over the parts list for the board and i’ll see about getting one. I found a SIA FPGA repo on github, might give us some jumping off points.
I appreciate your interest in the project. Kindly reread my original post, my intent is clearly stated there. This project is simply a proof of concept that equihash can be implemented on an Altera Cyclone V. It also facilitates an opportunity for me personally to learn about FPGA development. The intent was never to produce a piece of hardware to compete with ASICS or GPUs. I’m not selling any products or providing any software here, this is simply a project to prove a design and facilitate learning. If you are familiar with hardware design, please elaborate on your previous comment so that we can better understand the hardware requirements for an FPGA equihash miner. Saying something cannot be done without any details is not very helpful.
I’m not saying it can’t be done. You can do it quite readily with that hardware. The amount of data that must be accessed and manipulated in memory will be slow with that speed and bus width of memory. I’m not saying you shouldn’t do it if all you want is to learn. I am saying that your second goal will not be fulfilled
To create an affordable entry level FPGA that’s easy to use and lowers the startup cost for someone interested in equihash mining.
You will fail at this. This board costs too much and does too little. a $100 used GPU will exceed your results 10x+.
" I chose this board for it’s a lost cost and energy efficiency. "
You have picked a hardware solution seemingly without having even read and digested the requirements and limitations of the equihash algorithm. Further, you don’t need any hardware to write your HDL and simulate the performance and resources needed for it. You’re literally going about this backwards.
I’m not usually one to go out and criticize someone for their ideas, but you’re doing this thing that will ultimately be a waste of your time. I think you should revise your goals and reevaluate what you’re doing.
Thank you for the feedback, you sound pretty knowledgeable. How might you suggest I revise my goal? Honestly, I’m brand new to FPGA and I’m doing my best to try and understand everything. This project started out of a desire to learn FPGA development with a lack of funds to support it. I realize a DE10-nano is not a powerful board, but I’m really only doing this for the knowledge. What tools would you suggest I start using now to help me understand how to implement something like this? I appreciate any help or advice you can provide.
