Id love to help 
I have copied this from the ASIC thread to here, I think this is a better place to discuss this stuff.
When you say you are mining at the moment, what are you mining? I am pretty new to RandomX myself though.
If you can provide some more info on:
- CPU Make/Model
- Ram Frequency
- Ram type (ddr3/4)
- Ram Config (dual channel, etc)
- Ram timings.
- Ram Size
- Bios version and MB version
- CPU Microcode version.
With that info I can make a guess, and I can also give you some good parameters to get a rough idea with the benchmarking tool.
A lot of this in fact all of it (bar the microcode, that is a strange one to get depending on the cpu/mb) you can get from CPU-Z
If you open up CPU-Z, go to about, click on save as txt file.
Open the text file, then search for these headers
- Processors Information
- Thread dumps
- Chipset
- Memory SPD
You do not need to put all of the info from each section into your post. I have show the relevant data below.
If you use [details] brackets for the text it becomes expandable.
Here is an example of the report from the laptop above I have done the testing with. If you cannot get this report don’t worry too much but try to answer the first set of questions.
Would you mind running a few tests?
Test i7 Laptop
CPU-Z TXT Report
Processors Information
Processor 1 ID = 0
Number of cores 2 (max 2)
Number of threads 4 (max 4)
Name Intel Core i7 3540M
Codename Ivy Bridge
Specification Intel(R) Coreâ„¢ i7-3540M CPU @ 3.00GHz
Package (platform ID) Socket 1023 FCBGA (0x4)
CPUID 6.A.9
Extended CPUID 6.3A
Core Stepping E1/L1
Technology 22 nm
TDP Limit 35.0 Watts
Tjmax 105.0 °C
Core Speed 3487.9 MHz
Multiplier x Bus Speed 35.0 x 99.7 MHz
Stock frequency 3000 MHz
Instructions sets MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, EM64T, VT-x, AES, AVX
L1 Data cache 2 x 32 KBytes, 8-way set associative, 64-byte line size
L1 Instruction cache 2 x 32 KBytes, 8-way set associative, 64-byte line size
L2 cache 2 x 256 KBytes, 8-way set associative, 64-byte line size
L3 cache 4 MBytes, 16-way set associative, 64-byte line size
FID/VID Control yes
Thread dumps
CPU Thread 0
APIC ID 0
Topology Processor ID 0, Core ID 0, Thread ID 0
Type 01020101h
Max CPUID level 0000000Dh
Max CPUID ext. level 80000008h
Cache descriptor Level 1, D, 32 KB, 2 thread(s)
Cache descriptor Level 1, I, 32 KB, 2 thread(s)
Cache descriptor Level 2, U, 256 KB, 2 thread(s)
Cache descriptor Level 3, U, 4 MB, 16 thread(s)
Chipset
Northbridge Intel Ivy Bridge rev. 09
Southbridge Intel QM77 rev. 04
Memory Type DDR3
Memory Size 16 GBytes
Channels Dual
Memory Frequency 797.3 MHz (1:6)
CAS# latency (CL) 11.0
RAS# to CAS# delay (tRCD) 11
RAS# Precharge (tRP) 11
Cycle Time (tRAS) 28
Command Rate (CR) 1T
Host Bridge 0x0154
MCHBAR I/O Base address 0x0FED10000
MCHBAR I/O Size 19456
MCHBAR registers
Memory SPD
DIMM # 1
SMBus address 0x50
Memory type DDR3
Module format SO-DIMM
Manufacturer (ID) Kingston (7F980000000000000000)
Size 8192 MBytes
Max bandwidth PC3-12800 (800 MHz)
Part number 9905428-422.A00LF
Serial number 0B36C2B8
Manufacturing date Week 18/Year 15
Number of banks 8
Nominal Voltage 1.50 Volts
EPP no
XMP no
AMP no
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 5.0-5-5-14-19 @ 380 MHz
JEDEC #2 6.0-6-6-16-22 @ 457 MHz
JEDEC #3 7.0-7-7-19-26 @ 533 MHz
JEDEC #4 8.0-8-8-22-30 @ 609 MHz
JEDEC #5 9.0-9-9-24-33 @ 685 MHz
JEDEC #6 10.0-10-10-27-37 @ 761 MHz
JEDEC #7 11.0-11-11-28-39 @ 800 MHz
DIMM # 2
SMBus address 0x52
Memory type DDR3
Module format SO-DIMM
Manufacturer (ID) Kingston (7F980000000000000000)
Size 8192 MBytes
Max bandwidth PC3-12800 (800 MHz)
Part number 9905428-417.A00LF
Serial number 593A5631
Manufacturing date Week 13/Year 15
Number of banks 8
Nominal Voltage 1.35 Volts
EPP no
XMP no
AMP no
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 5.0-5-5-14-19 @ 380 MHz
JEDEC #2 6.0-6-6-16-22 @ 457 MHz
JEDEC #3 7.0-7-7-19-26 @ 533 MHz
JEDEC #4 8.0-8-8-22-30 @ 609 MHz
JEDEC #5 9.0-9-9-24-33 @ 685 MHz
JEDEC #6 10.0-10-10-27-37 @ 761 MHz
JEDEC #7 11.0-11-11-28-39 @ 800 MHz
I do see lots of potential avenues for hardware optimisation, along with hardsoftware (microcode - the stuff that defines what your cpu does, even L1/L2/L3 latencies) One currently very busy (not on this unfortunately) has a lot of experience with writing microcode and L1/L2 cache optimisation & design.
He is a long link on why microcode could make a massive difference for RandomX
Anyone serious about optimisation of RandomX mining hardware needs to read that. I will spare the link about Reverse Engineering it. (but that is linked in that article.)
Cheers.