You are welcome, after seeing how much afford and passion you put into your fpga design/work i thought to share this idea with you which gives you at least a chance to be competive and work toward a goal instead of chasing the asics.
Below a link to a equihash 150,5 miner. Beam, a new privacy crypto is currently using it and maybe this helps you with testing:
Good luck, would be nice if you keep this topic updated. Not that i understand all technical aspects, but at least me is curious how it works out at the end
true, it has been postponed yesterday. But than again he could mine BEAM meanwhile. Still better than competing against asics in my opinion and more promising for a FPGA made from scratch for equihashā¦
In best case when equihash 150,5 is released for ZEC he is ready and at least has a chance to mine at profitā¦
The FPGA miner is working. Finally got there, well happy and over the moon right now. My aim was to get it working first before optimising to make it faster.
Now you would think and FPGA miner would be quick, this isnāt yet. The hashing is done in the FPGA fabric and completes in around 0.1 seconds, the sorting is done in C on a 700Mhz processor, this will be moved into state machines so my limitation is with the DDR interface. Next will be a wider connection to DDR 64 or 128bit with 2gb or 4gb of DDR ram, Ready for the BEAM or the 150,5. Iāll need to build hardware for the DDR ram, it will take it as an SODIMM form.
Feels like i have created a child that is now finding its way in the world.
On a side note I found a guy who does bitstreams for FPGAs you may find useful http://zetheron.com
And not sure if your board is compatible but bittware has a free FPGA toolkit for tweaking stuff like voltages and so on https://www.bittware.com/fpga/toolkit-2/
Just out of curiousity and maybe an absolute stupid question, i hope you forgive me in such case.
Would it be possible to create some kind of, letās name it a āFPGA hybridā with parts from Asics and others from an FPGA? For example would it be possible to use the hashboards from equihash asics like the Z9 mini for example and attach them to an FGPA setup and make these working for example on other equihash algos like 150.5, 192.7, 144.5 and so on that way?
Wow, thatās some serious FPGA hardware, that would be a dream to work with some kit like that. Thanks for the link, interesting to see that stuff, a bit out of my price range.
The dev kit Iām working with is $200. However once Iām happy with the FPGA code Iāll migrate onto a new board using a similar FPGA but with no processor core, target cost of around $50 including DDR. Quite looking forward to designing the PCB for that, probably going to be an 8 layer board, I have done a tightly packed 6 layer board before. Then having multiples of these boards all attached to the main one to bring up the hashing rate and submit the results.
Good questionā¦
An FPGA is basically a programmable ASIC. So yes an FPGA could interface with the ASIC, if you knew the protocol, I guess that could be found out. I donāt know about the chips in the Z9 mini if the algo parameters can be changed. One hurdle for them is not having enough RAM if you chose the algo that needed more than they were designed for.
Which will be great when 2Gb or 2.5Gb of RAM is required, as ASICās will need to be redeveloped to work with this.
wouldnāt it be possible to use the RAM of the FPGA and eventually upgrade it to the needs? As said, total noob here, just some thoughts on the topic, lol.
The FPGA itself has little RAM inside, for a $30 FPGA we are looking at around 200 x 36kbits of RAM which is under 1Mbyte of RAM. Some larger chips do have over 10Mbyte for over $1000, but they still donāt have enough RAM. We need around 178Mbyte for 200,9, and even more for some others. An ASIC can be designed to have a lot of RAM inside, but it is very costly.
Say if you have a Z9 asic on board which used only internal RAM, there would be no way to expand that RAM, really it would need to be designed to use external RAM, there will be a speed loss with that, as internal block RAM is accessed in one clock cycle, where DDR needs around 10 DDR clock cycles to grab data as it take times to set up the address etc, of course data bursting helps you out, but you still canāt achieve the through put of internal RAM.
