Please explain to me how you can build an ASIC to “leave us in the dust”. You say you are in the industry. Do you understand the difference between the SHA256 proof of work and Equihash?
I submit that it is not possible to create an ASIC that would do so, unless someone found a vulnerability in the algorithm.
SHA256 is computation bound, thus an ASIC which doesn’t run an ILC could in theory produce a hash every clock cycle. You can’t do that with equihash-- unless you can fit 1GB of RAM on that ASIC, in which case you’re competing with DRAM vendors for performance.
Or, as I said, the DRAM is already the ASIC for EquiHash. Short of compromising the algorithm you’re not going to find a shortcut that lets you magically get significantly more performance, because performance is limited by memory bandwidth to a large amount of DRAM.